Logic Gates

Nand

Nand 门的逻辑描述为 out = not (a and b)
经过数学推理：

$$\begin{aligned} out & = \neg (a \wedge b) \\ & = relay_{on}(relay_{off}(a,b),V) \end{aligned}$$

故解法的VHDL描述为：

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-- 实体：nand 门
library ieee;
use ieee.std_logic_1164.all;

entity nand_gate is
    port (
        a, b : in  std_logic;  -- 输入
        y    : out std_logic   -- 输出 out = not (a and b)
    );
end nand_gate;

architecture struct of nand_gate is
    function relay_default_on(a_in, b_in : std_logic) return std_logic is
    begin
        return (not a_in) and b_in;
    end function;

    function relay_default_off(a_in, b_in : std_logic) return std_logic is
    begin
        return a_in and b_in;
    end function;

    signal temp : std_logic;
begin
    temp <= relay_default_off(a, b);
    y <= relay_default_on(temp, '1');
end struct;

Invert

Inv 门的逻辑描述为 out = not in
经过数学推理：

$$\begin{aligned} out & = \neg in \\ & = \neg (in \wedge in) \\ & = nand(in,in) \end{aligned}$$

故解法的VHDL描述为：

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-- 实体：inv 门
library ieee;
use ieee.std_logic_1164.all;

entity inv_gate is
    port (
        a : in  std_logic;  -- 输入
        y : out std_logic   -- 输出 out = not in
    );
end inv_gate;

architecture struct of inv_gate is

begin
    y  <= a nand a;
end struct;

And

And 门的逻辑描述为 out = a and b
经过数学推理：

$$\begin{aligned} out & = a \wedge b \\ & = \neg(\neg(a \wedge b))\\ & = inv(nand(in,in)) \end{aligned}$$

故解法的VHDL描述为：

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-- 实体：and 门
library ieee;
use ieee.std_logic_1164.all;

entity and_gate is
    port (
        a, b : in  std_logic;  -- 输入
        y    : out std_logic   -- 输出 out = a and b
    );
end and_gate;

architecture struct of and_gate is

begin
    y  <= not (a nand b);
end struct;

Or

Or 门的逻辑描述为 out = a or b
经过数学推理：

$$\begin{aligned} out & = a \vee b \\ & = \neg(\neg(a \vee b))\\ & = \neg(\neg a \wedge \neg b)\\ & = nand(inv(a),inv(b)) \end{aligned}$$

故解法的VHDL描述为：

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-- 实体：or 门
library ieee;
use ieee.std_logic_1164.all;

entity or_gate is
    port (
        a, b : in  std_logic;  -- 输入
        y    : out std_logic   -- 输出 out = a or b
    );
end or_gate;

architecture struct of or_gate is

begin
    y  <= (not a) nand (not b);
end struct;

Xor

Xor 门的逻辑描述为 out = ((not a) and b) or (a and (not b))
经过数学推理：

$$\begin{aligned} out & = (\neg a \wedge b) \vee (a \wedge \neg b) \\ & = (a \wedge \neg a) \vee (\neg a \wedge b) \vee (a \wedge \neg b) \vee (b \wedge \neg b)\\ & = (a \vee b) \wedge (\neg a \vee \neg b)\\ & = \neg (\neg a \wedge \neg b) \wedge \neg(a \wedge b)\\ & = \neg ((\neg a \wedge \neg b) \vee (a \wedge b))\\ & = \neg ((\neg a \wedge \neg b) \vee ((a \wedge b) \wedge (\neg a \vee \neg b \vee 1)))\\ & = \neg ((\neg a \wedge \neg b) \vee ((a \wedge b) \wedge \neg a)) \vee ((a \wedge b) \wedge \neg b) \vee (a \wedge b)\\ & = \neg ((\neg a \wedge \neg b) \vee ((a \wedge b) \wedge \neg a)) \vee ((a \wedge b) \wedge \neg b) \vee ((a \wedge b) \wedge (a \wedge b))\\ & = \neg ((\neg a \vee (a \wedge b)) \wedge (\neg b \vee (a \wedge b)))\\ & = \neg (\neg (a \wedge \neg (a \wedge b)) \wedge \neg (b \wedge \neg (a \wedge b)))\\ & = nand(nand(a,nand(a,b)),nand(b,nand(a,b))) \end{aligned}$$

推导过程让我回忆起了：$a+b=1$，求$\frac{1}{a}+\frac{1}{b}$的最小值。

故解法的VHDL描述为：

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-- 实体：xor 门
library ieee;
use ieee.std_logic_1164.all;

entity xor_gate is
    port (
        a, b : in  std_logic;  -- 输入
        y    : out std_logic   -- 输出 out = a xor b
    );
end xor_gate;

architecture struct of xor_gate is
signal s,m,n : std_logic;
begin
    s <= a nand b;
    m <= a nand s;
    n <= b nand s;
    y <= m nand n;

end struct;

文章完

你完成了NandGame-Computer-Logic_gates章节！